Digital integrated circuit chips are composed of many millions of gates that make up various functional components on a chip such as flip-flops, multiplexors, logic circuits, etc. A given chip design may have thousands of flip-flops scattered throughout the chip.
In order to effectively and efficiently test a given chip, certain test features are typically incorporated into the chip design for testing purposes. Before a chip is actually taped out and manufactured, the chip design is first simulated in software using various simulation tools such as, for example, a Verilog Test Bench. By simulating the design of the chip, the design features of the chip may be thoroughly tested before the expense and time of actually manufacturing the chip is incurred.
Pattern verification is a critical phase in testing of chips. A scan pattern is a digital string of binary ones and zeros that may be shifted through a scan chain of flip-flops in the chip design. Every scan pattern cycle is composed of two phases. The first phase is the load_unload phase where new data is shifted into the scan chains of flip-flops. The second phase is the capture phase where the data is captured into the flip-flops by applying a clock pulse.
Typically, the flip-flops in a digital integrated circuit design are designed such that they have normal data inputs and outputs (D and Q) and test inputs such as TI (test data input) and TE (test enable input). During simulation, the flip-flops may be placed in the test mode by enabling the TE input. Data may then be clocked into the flip-flops through the TI input instead of the normal D data input. During testing, the flip-flops of the chip are chained together to form multiple scan chains. The output Q of a given flip-flop is connected to the input TI of a next flip-flop. Each scan chain may comprise, typically, 5000 to 10,000 flip-flops.
The length of the load_unload phase is equal to the length of the longest scan chain of flip-flops. In multimillion gate designs, the longest chain may have thousands of flip-flops. Most of the time, simulating the scan patterns through the scan chains is spent shifting the data into and out of the scan chains. To ensure proper behavior of the scan chains, the first test applied to the chip design is Chain Test which consists of shifting in and out a predetermined bit pattern (e.g. 0011).
FIG. 1. illustrates the timing operation of a flip-flop within a chip design. In order for a flip-flop to capture data at its output Q when presented at its input D (or TI during test mode), the data must be present at the input D (or TI) for a setup time 10 before the clock edge 20 comes along to clock the data into the flip-flop. Also, the data must be held steady at the input D (or TI) for a hold time 30 to ensure the data is properly clocked into the flip-flop and appears at the output Q. The setup time 10 may typically be around 200 picoseconds and the hold time 30 may typically be around 100 picoseconds. Together, the setup time 10 and the hold time 30 make up the setup-and-hold window 40. If the data at input D (or TI) of a flip-flop changes during the setup-and-hold window 40, then the resultant output at Q cannot be guaranteed.
FIG. 2 illustrates an example where a particular type of error may occur in a scan chain. The error is called a double shift error and is caused by an excessive delay between the clock inputs of two successive, contiguous flip-flops within a scan chain. If the clock signal for flip-flop 3 (FF3) is delayed too much compared to the clock signal for flip-flop 2 (FF2), then the data shifted into FF2 will be captured in FF3 in the same clock cycle (see waveform Q(3) wrong). Q(2) becomes a ‘1’ before the previous Q(2)=0 state can get clocked into FF3 (i.e., Q3 becomes ‘1’instead of ‘0’ as it should if the timing were correct). Such behavior translates into scan pattern failures.
If the skew between the two clock destinations (FF2 and FF3) is within the setup-and-hold window 40, then any failure will appear as a timing violation within the simulation land a symbol X will be captured for the faulty flip-flop (FF3). However, if the skew is wider than the setup-and-hold window, then the failure constitutes a double shift error between the two flip-flops.
A timing violation error message in the simulation contains enough information to identify the faulty flip-flop but the double shift error is more challenging to debug. In other words, isolating the double shift error to two flip-flops can be difficult and time consuming. The mismatch caused by the double shift error first appears at the output of the scan chain after N cycles where N is the number of flip-flops in the longest scan chain. Since the data is shifted through thousands of flip-flops, there is no indication of where the double shift error may have occurred. In order to find the source of the mismatch (i.e. the two flip-flops), it is often necessary to look at thousands of clock and data waveforms across thousands of clock cycles. This is very time consuming and prone to error.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.